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NB4N855S 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevel input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin-for-pin plug in compatible to the SY55855V in a 3.3 V applications. The NB4N855S has a wide input common mode range of GND + 50 mV to VCC - 50 mV. This feature is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels. The device is offered in a small 10 lead MSOP package. NB4N855S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements. Application notes, models, and support documentation are available at www.onsemi.com.
Features
http://onsemi.com MARKING DIAGRAM*
10 1 Micro-10 M SUFFIX CASE 846B A Y W G 855S AYWG G 1 = Assembly Location = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
* * * * * * * * *
Guaranteed Input Clock Frequency up to 1.0 GHz Guaranteed Input Data Rate up to 1.5 Gb/s 490 ps Maximum Propagation Delay 1.0 ps Maximum RMS Jitter 180 ps Maximum Rise/Fall Times Single Power Supply; VCC = 3.3 V 10% Temperature Compensated TIA/EIA-644 Compliant LVDS Outputs GND + 50 mV to VCC - 50 mV VCMR Range Pb-Free Package is Available
D0 D0
Q0 Q0
D1 D1
Q1 Q1
Functional Block Diagram
VOLTAGE (50 mV/div)
ORDERING INFORMATION
Device DDJ = 7 ps
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5 (VINPP = 100 mV, Input Signal DDJ = 24 ps)
(c) Semiconductor Components Industries, LLC, 2006
April, 2006 - Rev. 2
1
Publication Order Number: NB4N855S/D
NB4N855S
D0 D0 D1 D1 GND
1 2 3 4 5
10 9 8 7 6
VCC Q0 Q0 Q1 Q1
Figure 2. Pin Configuration and Block Diagram (Top View)
Table 1. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 Name D0 D0 D1 D1 GND Q1 Q1 Q0 Q0 VCC I/O LVPECL, CML, LVCMOS, LVTTL, LVDS LVPECL, CML, LVCMOS, LVTTL, LVDS LVPEL, CML, LVDS LVCMOS, LVTTL LVPECL, CML, LVDS LVCMOS LVTTL - LVDS Output LVDS Output LVDS Output LVDS Output - Description Noninverted Differential Clock/Data D0 Input. Inverted Differential Clock/Data D0 Input. Noninverted Differential Clock/Data D1 Input. Inverted Differential Clock/Data D1 Input. Ground. 0 V. Inverted Q1 output. Typically loaded with 100 W receiver termination resistor across differential pair. Noninverted Q1 output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted Q0 output. Typically loaded with 100 W receiver termination resistor across differential pair. Noninverted Q0 output. Typically loaded with 100 W receiver termination resistor across differential pair. Positive Supply Voltage.
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Table 2. ATTRIBUTES
Characteristics Moisture Sensitivity (Note 1) Micro-10 Flammability Rating ESD Protection Oxygen Index: 28 to 34 Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Value Pb-Free Pkg Level 1
UL 94 V-0 @ 0.125 in > 2 kV > 200 V > 1 kV 281
Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol VCC VI IIN IOSC Parameter Positive Power Supply Positive Input Input Current Through RT (50 W Resistor) Output Short Circuit Current Line-to-Line (Q to Q) Line-to-End (Q or Q to GND) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 2) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 1S2P (Note 4) <3 Sec @ 248C <3 Sec @ 260C Micro-10 Micro-10 Micro-10 Condition 1 GND = 0 V GND = 0 V Static Surge Q or Q to GND Q to Q Micro-10 Continuous Continuous VI = VCC Condition 2 Rating 3.8 3.8 35 70 12 24 -40 to +85 -65 to +150 177 132 40 265 265 Unit V V mA mA mA
TA Tstg qJA qJC Tsol
C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board - 1S2P (1 signal, 2 power).
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Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = -40C to +85C
Symbol ICC Vth VIH VIL VIHD VILD VCMR VID VOD DVOD VOS DVOS VOH VOL Power Supply Current (Note 3) Characteristic Min Typ 40 Max 53 Unit mA
DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Figures 10 and 12) Input Threshold Reference Voltage Range (Note 4) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage GND +100 Vth + 100 GND VCC - 100 VCC Vth - 100 VCC VCC - 100 VCC - 50 VCC 450 1.0 25 1375 1.0 1425 900 1075 25 1600 mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11 and 13) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) Differential Input Voltage (VIHD - VILD) Differential Output Voltage Change in Magnitude of VOD for Complementary Output States (Note 6) Offset Voltage (Figure 9) Change in Magnitude of VOS for Complementary Output States (Note 6) Output HIGH Voltage (Note 7) Output LOW Voltage (Note 8) 100 GND GND + 50 100 mV mV mV mV
LVDS OUTPUTS (Note 5) 250 0 1125 0 mV mV mV mV mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Dx/Dx at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 4. Vth is applied to the complementary input when operating in single-ended mode. 5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 8. 6. Parameter guaranteed by design verification not tested in production. 7. VOHmax = VOSmax + 1/2 VODmax. 8. VOLmax = VOSmin - 1/2 VODmax.
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Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 9)
-40C Symbol VOUTPP fDATA tPLH, tPHL tSKEW Characteristic Output Voltage Amplitude (@ VINPPMIN) fin 1.0 GHz (Figure 3) fin= 1.5 GHz Maximum Operating Data Rate Differential Input to Differential Output Propagation Delay Duty Cycle Skew (Note 10) Within -Device Skew (Note 11) Device to Device Skew (Note 12) RMS Random Clock Jitter (Note 13) Deterministic Jitter (Note 14) Crosstalk Induced Jitter (Note 15) VINPP tr tf fin = 1.0 GHz fin = 1.5 GHz fDATA = 622 Mb/s fDATA = 1.5 Gb/s fDATA = 2.488 Gb/s 100 Q, Q 50 110 Min 230 200 1.5 330 Typ 350 300 2.5 410 8 10 20 0.5 0.5 6 7 10 20 490 45 35 100 1 1 15 20 25 40 VCC- GND 180 100 50 110 Max Min 230 200 1.5 330 25C Typ 350 300 2.5 410 8 10 20 0.5 0.5 6 7 10 20 490 45 35 100 1 1 15 20 25 40 VCC- GND 180 100 50 110 Max Min 230 200 1.5 330 85C Typ 350 300 2.5 410 8 10 20 0.5 0.5 6 7 10 20 490 45 35 100 1 1 15 20 25 40 VCC- GND 180 Max Unit mV Gb/s ps ps
tJITTER
ps
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 16) Output Rise/Fall Times @ 250 MHz (20% - 80%)
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPPMIN with 50% duty cycle clock source and VCC - 1400 mV offset. All loading with an external RL = 100 W across "D" and "D" of the receiver. Input edge rates 150 ps (20%-80%). 10. See Figure 7 differential measurement of tskew = |tPLH - tPHL| for a nominal 50% differential clock input waveform @ 250 MHz. 11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition. 12. Skew is measured between outputs under identical transition @ 250 MHz. 13. RMS jitter with 50% Duty Cycle clock signal. 14. Deterministic jitter with input NRZ data at PRBS 223-1 and K28.5. 15. Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 -1 as an asynchronous signals. 16. Input voltage swing is a single-ended measurement operating in differential mode.
400 OUTPUT VOLTAGE AMPLITUDE (mV) 350 300 250 200 150 100 50 0 85C 25C -40C
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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NB4N855S
VOLTAGE (50 mV/div)
Device DDJ = 6 ps
VOLTAGE (50 mV/div)
Device DDJ = 6 ps
TIME (322 ps/div)
TIME (322 ps/div)
Figure 4. Typical Output Waveform at 1.5 Gb/s with 223-1 (VINPP = 100 mV (left) & VINPP = 400 mV (right), Input Signal DDJ = 24 ps)
VOLTAGE (50 mV/div)
Device DDJ = 10 ps
VOLTAGE (50 mV/div)
Device DDJ = 10 ps
TIME (80 ps/div)
TIME (80 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with 223-1 (VINPP = 100 mV (left) & VINPP = 400 mV (right), Input Signal DDJ = 30 ps)
RC 1.25 kW Dx 1.25 kW I
RC 1.25 kW
1.25 kW
Dx
Figure 6. Input Structure
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NB4N855S
D D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH VINPP = VIH(D) - VIL(D)
Figure 7. AC Reference Measurement
LVDS Driver Device
Q
Zo = 50 W 100 W
D
LVDS Receiver Device
Q
Zo = 50 W
D
Figure 8. Typical LVDS Termination for Output Driver and Device Evaluation
QN VOS QN VOD
VOH
VOL
Figure 9. LVDS Output
VIH VIL Vth
D
D
Vth
D
D
Figure 10. Differential Input Driven Single-Ended
Figure 11. Differential Inputs Driven Differentially
VCC Vthmax VCC D Vth Vthmin GND VIHmin D VILmin VEE VIHmax VILmax VCMR
VIH(MAX) VIL VIH VINPP = VIHD - VILD VIL VIH VIL(MIN)
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
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NB4N855S
ORDERING INFORMATION
Device NB4N855SMR4 NB4N855SMR4G Package Micro-10 Micro-10 (Pb-Free) Shipping 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D
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NB4N855S
PACKAGE DIMENSIONS
Micro-10 CASE 846B-03 ISSUE D
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION "A" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION "B" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B-01 OBSOLETE. NEW STANDARD 846B-02 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028
K
-B-
PIN 1 ID
G
D 8 PL 0.08 (0.003)
M
TB
S
A
S
0.038 (0.0015) -T-
SEATING PLANE
C H J L
SOLDERING FOOTPRINT*
10X
1.04 0.041
0.32 0.0126
10X
3.20 0.126
4.24 0.167
5.28 0.208
8X
0.50 0.0196
SCALE 8:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
AnyLevel is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB4N855S/D

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